Hardware Reference
In-Depth Information
The latter implementation is usually more efficient because it replaces a three-bit
free variable with a one-bit free variable. FV efficiency significantly decreases with
each free bit added. Another advantage is that using free variables in assignments is
more efficient than in assumptions
t
The situation with passing free variables to functions is similar. Though it is
illegal to declare free variables within a function, either in a function body or among
function ports, it is legal to pass free variables to a function, as illustrated in the
following example.
Example 23.16.
The following code may be used to find a maximum among two
free variables of size
N
, where
N
is an elaboration-time constant.
rand bit
[N] v1, v2;
function bit
[N] max(
bit
[N]a,b);
if
(a >= b)
return
a;
return
b;
endfunction
: max
Though function
max
operates with regular variables only, it is legal to pass free
variables
v1
and
v2
to it.
t
Why is it forbidden to assign free variables by continuous or blocking assign-
ment? The main reason is that it is difficult to define acceptable simulation semantics
in this case (see Sect.
23.3
). There is also a problem of combinational loops.
Consider, for example, the following illegal code:
rand bit
a, b;
bit
c;
// c assigned elsewhere
assign
a=~b&c;
assign
b= a&c;
If
c
changes from
0
to
1
then it is completely unclear what should happen with
a
and
b
.
Note that the same problem exists if
a
and
b
are defined as regular variables. In
simulation this causes an infinite iteration. This is why in SystemVerilog 2009 it
was illegal to use any continuous or blocking assignments in checkers. However,
this problem also exists in modules, interfaces and programs. It is usually solved at
a tool level. Simulators may detect an infinite iteration, abort it and issue an error
message. Synthesis and FV tools detect combinational loops statically.
7
Because the
problem is not specific to checkers, SystemVerilog 2012 relaxes the restrictions and
allows continuous and blocking assignments to regular variables in checkers.
A contention problem, when the same variable is assigned in different processes,
does not exist in checkers. If a variable is assigned in one checker process it cannot
7
Simulators may also do this.
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