Hardware Reference
In-Depth Information
:
i
^:
o
^:
i
0
^
o
0
_
:
i
^:
o
^
i
0
^
o
0
_
i
^:
o
^
i
0
^:
o
0
_
i
^:
o
^:
i
0
^:
o
0
_
:
i
^
o
^:
i
0
^
o
0
_
:
i
^
o
^
i
0
^
o
0
_
i
^
o
^
i
0
^:
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0
_
i
^
o
^:
i
0
^:
o
0
D
:
i
^:
o
^
o
0
_
i
^:
o
^:
o
0
_
:
i
^
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o
0
_
i
^
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^:
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0
D
.
:
i
^
o
0
/
_
.i
^:
o
0
/
D
i
˚
o
0
To understand how this symbolic representation is obtained, consider the state
f
i
g
as an example. From Fig.
21.3
, there are two transitions from
f
i
g
:
f
i
g!f
i
g
, and
f
i
g!;
. To symbolically represent the transition
f
i
g!f
i
g
, we encode
f
i
g
from
the source of the transition with the current state variables and
f
i
g
from the target of
the transition with the next state variables, and then form a conjunction. This yields
i
^:
o
^
i
0
^:
o
0
. Similarly, the symbolic encoding of the transition
f
i
g!;
is
i
^:
o
^:
i
0
^:
o
0
. The set of these two transitions is represented as a disjunction
.i
^:
o
^
i
0
^:
o
0
/
_
.i
^:
o
^:
i
0
^:
o
0
/. Although the further transformations
simplifying the characteristic function of the transition relation are routine, it is
instructive to understand an interpretation of these transformations. For example,
i
^:
o
^
i
0
^:
o
0
_
i
^:
o
^:
i
0
^:
o
0
D
i
^:
o
^:
o
0
means that all the transitions from
state
f
i
g
lead to states where o is false. This agrees with the behavior of module
m
:
if the current value of i is high then the next value of o is low.
The series of simplifications yields a compact formula for the entire transition
relation: i
˚
o
0
. This result expresses the essence of the whole model: the next value
of o is the negation of the current value of i .
t
21.2.3.1
Sampled Value Functions
The next state
v
0
of a variable
v
2
V may be interpreted as the value of
v
in the next tick of the global clock, and therefore in SystemVerilog
v
0
corre-
sponds to
$future_gclk(v)
. Using global clocking future sampled value functions
(Sect.
7.2.2.2
), it is possible to explicitly express a transition relation in System-
Verilog.
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