Coverage - SVA: The Power of Assertions in SystemVerilog - page 418

parameter N=4;

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property path_cover(inIdx, outIdx, sourceId, destId);

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@( posedge clkIn)

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(startIn[inIdx] && sourceId == dataIn[inIdx]) ##1

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(destId == dataIn[inIdx])

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##0

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@( posedge clkOut)

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(startOut[outIdx] && dataOut[outIdx] == sourceId) ##1

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(dataOut[outIdx] == destId);

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endproperty

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generate

for ( genvar pIn = 0; pIn < N; pIn++) begin : PORT_IN

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for ( genvar pOut = 0; pOut < N; pOut++) begin : PORT_OUT

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for ( genvar sId = 0; sId < 256; sId++) begin : SOURCE_ID

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for ( genvar dId = 0; dId < 256; dId++) begin : DEST_ID

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cover_path:

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cover property (path_cover(pIn, pOut, sId, dId));

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end

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end

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end

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end

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endgenerate

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Fig. 18.2 Coverage using generate loops

packet path coverage for this 4 4 switch will generate 4 4 256 256 D 2 20
cover properties, all running at the same time.
Perhaps it is not necessary to track all source and destination IDs, hence the
number of cover properties can be reduced. Still, the overhead may be large.
A better and more elegant solution can be obtained by combining N cover property
statements, one for each output port of the switch, with a covergroup that collects
the coverage of paths. This is shown in Fig. 18.3 .
The combination of N cover properties with a single covergroup provides a
speed up of up to 2 18 for a 4 4 switch over the simplistic solution using nested
generate loops. Furthermore, the coverage report generated for the covergroup will
nicely summarize which paths were covered and how many times. This is due to the
cross statement in the covergroup .

t

Exercises

18.1. For Example 18.13 , write a cover property that records that a retry
occurred.

18.2. For Example 18.13 , write several cover property statements that record

the number of retries that occurred (from 1 to 3).