Coverage - SVA: The Power of Assertions in SystemVerilog - page 416

We can now enhance the checker in Fig. 1.6 to include collection of coverage
information to make sure that the behavior of the design is sufficiently exercised by
simulation tests. The enhancements are shown in Fig. 18.1 .
Property tx_rx_ack describes a situation in which a packet sent of the type
kind_t having a particular tag eventually receives an acknowledgment. The corre-
spondence between the sending packet tag and the acknowledged tag is assured by
using the local variable tag in the property. It is assigned the tag of the transmitted
packet at the time when sent is true and then checked when an acknowledgment
arrives. Only when the tags match does the property succeed, and then the coverage
count in the database is incremented.

t

The next example illustrates another important point regarding the combined
power of cover property and the covergroup construct. It shows that this
scheme can save on coding effort, reduce simulation time, and consolidate reporting.
The example uses a simplified N N switch.

Example 18.14. A switching device has N 256 8-bit input ports and N 256
8-bit output ports arranged in packed arrays:
logic [N-1:0] [7:0] dataIn ;
logic [N-1:0] [7:0] dataOut ;
A packet consists of 256 8-bit bytes. Each packet enters the switch on one of
the input ports and leaves the switch on one of the output ports. Packet data is
transmitted one byte at a time across a port. The first byte of a packet contains the
source ID where the packet originated. The second byte contains the destination
ID where the packet is to be routed after it leaves the output port. A 1-bit signal is
associated with each input and output port indicating the start of a packet. Vector
bit [N-1:0] startIn is used for input ports, while bit [N-1:0] startOut is
used for output ports. Bit i of either port is set to one when the first byte arrives.
At all other times the bits are set to 0. The incoming data are all synchronized to
posedge clkIn , the outgoing data are synchronized to posedge clkOut . There is
a delay of at least 2 clkIn cycles before a packet can emerge on an output port. For
simplicity, we assume more specifically that the first byte of a packet will appear on
one of the output ports at the first posedge of clkOut at or after the posedge of clkIn
when the second byte of the packet appeared on its input port.
It is required to construct a coverage collection system such that correlated
information is collected about which source ID and destination ID appeared in a
packet, together with the input port and output port through which the packet was
routed in the switch.

Discussion: A simple approach is to define a property that characterizes one path
of a packet from one input port to one output port, and use a generate loop to build
as many instances of a cover property as there are possible combinations of paths
through the switch and IDs. This is shown in Fig. 18.2 .
While the definition of this coverage model is quite concise and simple to encode,
it will impose a heavy burden on the simulator and will most likely produce a
coverage report that is long and difficult to analyze. Even with a small N D 4,the