Coverage - SVA: The Power of Assertions in SystemVerilog - page 410

There are many variations on how to define parameterized covergroups, bins,
crosses, conditional selection, etc. They are beyond the scope of this topic, but the
information provided here should be sufficient to illustrate their combined power
with assertions.

18.2.4 Combining Covergroups and Assertions

We can use a covergroup to collect information on the delays in Example 18.5 .
The generate loop in that example can be disposed of as follows:

Example 18.7.
default clocking ck @( posedge clk); endclocking
covergroup delay_cg
with function sample( int unsigned delay);
dl_pt: coverpoint delay {
bins delays [100]: {[1:100]};

}
endgroup
delay_cg delay_cg_inst = new ();
property p_delay_coverage;
int unsigned ticks_l;
disable iff (reset)
(a, ticks_l = 0)
#-# (ticks_l < 100, ticks_l++)[+]
##1 (
b,
delay_cg_inst.sample(ticks_l), // match item
$display("prop_cov4 success, time %t, delay %0d",
$time, ticks_l)

// match item

);
endproperty
prop_cov4: cover property (p_delay_coverage);

t

The main components of this form of coverage collection are:

￿ covergroup delay_cg definition that specifies a coverpoint on the formal
argument of the method sample .
￿A covergroup instance delay_cg_inst that creates the actual coverage object.
￿ A cover on property p_delay_coverage , which uses a local variable ticks_l of
the same type as the formal argument of the sample method to count the number
of clock ticks until b matches.
￿ When b matches, sample is called to classify the current value of the local
variable in the coverage database.

Whenever prop_cov4 is triggered by the occurrence of a , the local variable
ticks_l is initialized to 0. ticks_l is incremented at each clock tick thereafter
until b occurs, provided it is within 100 clock ticks. When b matches, sampling of
tick_l by the covergroup takes place. The coverage database thus has two entries,