Coverage - SVA: The Power of Assertions in SystemVerilog - page 402

Chapter 18
Coverage

Verification may not ever be complete, but we should know what
was verified.

— Unknown.

An important mechanism for determining whether design validation has sufficiently
verified the design on hand is to collect “coverage” information, both structural and
functional. This chapter describes how assertions can be used to gather functional
coverage information using cover property and cover sequence statements.
It is mainly suitable to collect information about the occurrences (or not) of some
sequences of events. SystemVerilog provides another mechanism for collecting
coverage, called covergroups . They are particularly suitable for gathering infor-
mation about the occurrence of data patterns and their cross correlation. Often, it
is important to detect a particular sequence of events and then initiate collecting
coverage on data patterns. This can be achieved by combining assertion coverage
with that of covergroups.
As we have seen, assertions and assumptions provide a precise way to state
functional specification of a design and its environment. While these assertion
statements may nonvacuously pass in our tests, we may still find that the design
contains errors. Why is that? The answer is quite simple: In simulation, we may have
not exercised all functional modes of the design, and the bugs may be hiding there.
In formal verification which is exhaustive with respect to each assertion, the problem
may lie in the fact that the assumptions representing the behavior of the environment
are more strict than the actual usage of the design, or because the search space was
restricted due to memory limitations. In either situation, we should have means to
determine the extent to which the design functionality has been exercised. There
are essentially two main methods for measuring this extent: Code Coverage and
Functional Coverage . Code coverage is concerned with measuring the percentage
of lines of code executed, which conditional blocks were executed and caused by
which conditions, etc. These measures indicate how much the implementation was