Mechanics of Local Variables - SVA: The Power of Assertions in SystemVerilog - page 380

1. sequence s1( bit a, b, c);
bit l_b;
(a, l_b = b) throughout c[->1];
endsequence

2. sequence s2( bit a, b, c);
bit l_b;
a throughout (c, l_b = b)[->1];
endsequence

3. sequence s3;
byte l_numBeats;
(start, l_numBeats = numBeats) ##1
(

(dataValid[->1])[ * l_numBeats] ##1 !dataValid[ * ]
intersect
complete[->1]

);
endsequence

16.3. Explain why the following is not legal:

sequence s_illegal( local input bit l_a, l_b = l_a);
bit l_c, l_d = l_c;
(t, l_c = l_a) ##1 {l_a,l_b} != {l_c,l_d};
endsequence

16.4. For each of the following declarations, analyze the local variable flow and
determine whether any references to local variables are illegal. Use rules of local
variable flow to justify your analysis.

1. sequence s1;
byte l_v;
a ##1 (b, l_v &= e);
endsequence

2. property p2;
byte l_v;
(a, l_v = e)
|->
s_nexttime s_eventually (b == l_v);
endproperty

3. property p3;
byte l_v;
(a, l_v = e)
implies
s_nexttime s_eventually (b == l_v);
endproperty

4. property p4;
bit [1:0] l_v = e;