Mechanics of Local Variables - SVA: The Power of Assertions in SystemVerilog - page 359

Here is an example of legal declarations illustrating this capability and the
restrictions:
sequence s3(
local input byte l_a, l_b,
local input byte l_c[8],
local input byte l_d,
local inout byte l_e,
local input bit l_f,
local input bit [0:3] l_g, l_h
);
...
endsequence
l_a and l_b are both of direction input and data type byte . l_c is of direction
input and is an unpacked array of eight bytes. Because of the unpacked dimension,
the declaration of l_c cannot share the keyword local and direction with either
the preceding or the subsequent declaration. Because the direction of l_e does not
match the preceding direction, the declaration of l_e must specify the keyword
local and the direction and data type. l_g and l_h are both packed vectors of
4 bits. Even though l_g has the same direction and base data type as l_f ,ithas
different packed dimension and so must have its own specification of the keyword
local , direction, and data type. 5
An input argument local variable may be declared with an optional default
actual argument, which can be any expression that may be assigned to the argument
local variable. An output or inout argument local variable may not be given a
default actual argument because the actual argument must specify the local variable
that will receive the output value. The syntax for a default actual argument is
the same as that for ordinary formal arguments of sequences or properties (see
Sect. 8.2 ). The default actual argument serves as the actual argument in any instance
of the sequence or property that does not otherwise specify the actual argument. As
usual, names in the default actual argument expression resolve in the context of the
sequence or property declaration, not in the context of its instantiation. Here is a
modification of property p1 that specifies a default actual argument:
property p1_v3( local input byte l_byte = data);
byte l_byteMasked = l_byte & mask;
...
endproperty
The default actual argument for l_byte is data .
5 The rules of sharing components of declarations are more stringent than necessary. Future versions
of SystemVerilog may relax them.