Hardware Reference
In-Depth Information
property
p_mult_leading_clks;
1
byte
l_v = e;
2
(@(
posedge
clk1) a1
until
b1 == l_v)
3
and
4
(@(
posedge
clk2) a2
until
b2 == l_v);
5
endproperty
6
Fig. 16.1
Property with local variable declaration assignment and multiple leading clocks
l_v = e
for the second is performed in the first time step concurrent or subsequent
to t
0
in which
posedge
clk2
occurs. The behavior of
p_mult_leading_clks
is
therefore equivalent to the following variant, in which the declaration assignment
has been eliminated:
property
p_mult_leading_clks;
1
byte
l_v;
2
(@(
posedge
clk1) (1'b1, l_v = e) #-# a1
until
b1 == l_v)
3
and
4
(@(
posedge
clk2) (1'b1, l_v = e) #-# a2
until
b2 == l_v);
5
endproperty
6
16.2
Declaring Argument Local Variables
The preceding section presented the following example:
sequence
s2(
logic
start, b[4]);
logic
l_a = 1'b0, l_b[4] = b;
dataType l_data;
@(
posedge
clk)
start ##1 ... // assume no further reference to b
endsequence
The body local variable
l_b
has a declaration assignment whose entire right-hand
side is a reference to the like-typed formal argument
b
. The declaration assignments
are performed when the evaluation reaches alignment with
posedge
clk
, and at that
point the value in the formal argument
b
is assigned to
l_b
. Assume that the body of
s2
makes no further reference to
b
. Then the sole use of this formal argument is to
provide the local variable
l_b
its initial value, which is determined from the actual
argument expression associated with
b
in the relevant instance of
s2
.
In such a case, it is convenient to be able to declare the formal argument itself as a
local variable. SystemVerilog provides this capability in
argument local variables
.
4
Under the assumption that the only reference to
b
in
s2
is in the declaration
assignment to
l_b
, the following variant is semantically equivalent to
s2
:
4
In the LRM[
8
], argument local variables are called local variable formal arguments.
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