Mechanics of Local Variables - SVA: The Power of Assertions in SystemVerilog - page 354

Unlike other SystemVerilog variables, local variables have no default initial
values. A body local variable may optionally be declared with a declaration
assignment . Declaration assignments are also called initialization assignments
because in each evaluation they provide the initial values to the associated local
variables. Consider the following example:
sequence s2( logic start, b[4]);
logic l_a = 1'b0, l_b[4] = b;
dataType l_data;
@( posedge clk)
start ##1 ...
endsequence
The local variables l_a and l_b have declaration assignments. The expression on
the right-hand side of a declaration assignment can be any expression that may be
assigned to the local variable. It need not be constant. For a given evaluation of
s2 , the declaration assignments are performed in the first time step in which there
is an occurrence of the leading clocking event, posedge clk . At that point, l_a
is assigned the value 1'b0 and l_b is assigned the value of the unpacked array
formal argument b . The local variable l_data , however, has no value at that point
and is said to be unassigned . If evaluation of s2 begins in a time step in which
posedge clk has occurred, then the declaration assignments are performed at that
point. 2
Evaluation of the right-hand side of a declaration assignment follows the rules
for evaluation of the right-hand side of an ordinary local variable assignment, as
discussed in Sect. 16.3 . The delay, as necessary, of the performance of a declaration
assignment until occurrence of the leading clocking event of the sequence or
property implies that these assignments are semantically equivalent to ordinary local
variable assignments performed at the appropriate points. For example, s2 above is
semantically equivalent to the following variant:
sequence s2_v2( logic start, b[4]);
logic l_a, l_b[4];
dataType l_data;
@( posedge clk)
(start, l_a = 1'b0, l_b[4] = b) ##1 ...
endsequence
The local variable declaration assignments have been moved and attached to the first
Boolean expression, start , of the sequence. Alternate interpretation is prefixing the
original sequence using ##0 :
sequence s2_v2( logic start, b[4]);
logic l_a, l_b[4];
dataType l_data;
2 In a singly clocked setting, where all timing is aligned to the same clocking event, evaluation of a
sequence or property always begins in a time step in which the clocking event has occurred.