Introduction - SVA: The Power of Assertions in SystemVerilog - page 17

Clock Domain Crossing When data are transferred from a state element controlled
by one clock to a state element controlled by another clock the data should be
stable long enough to guarantee that it be sampled by the second clock [ 54 ].
Multicycle Path A multicycle path is a path between two state elements having a
delay greater than one clock cycle. A multicycle path permits the sum of the
delays of its combinatorial logic elements to be greater than one clock cycle.
In this case, the second state element should be stable during the corresponding
number of clock cycles [ 15 ].

We also mention the need for analog assertions [ 52 ] to specify the timing
behavior of electrical components and interconnections. This type of assertion is
specific to analog circuit analysis and performance verification, and it is currently
not part of SVA. We do not discuss it further in this topic.

Post-Silicon Validation

The advantages of RTL verification, on the one hand, are flexibility and high
observability—all signal values at any time may be observed in simulation. On the
other hand, it is very slow, and does not allow checking many important global
scenarios. With post-silicon validation (and to a great extent in emulation) the
situation is the opposite: chip speed is very high, but signal observability is low
[ 11 , 57 , 65 ].
Postsilicon debugging is challenging because a bug can remain unobserved for
millions of cycles after its actual occurrence. ABV may help coping with this
problem. For example, the most critical RTL assertions may be synthesized into the
chip. Assertions fire immediately upon detecting an error, thus making bug detection
and debugging much more efficient.

1.3 Assertions in SystemVerilog

There are three kinds of assertions in SystemVerilog 7 :

￿ Immediate assertions
￿ Deferred assertions
￿ Concurrent assertions

7 Our terminology for the kinds of assertions matches what we hear customarily in practice, but it
differs from the terminology in the SystemVerilog 2012 LRM. What we call “immediate” is called
“simple immediate” in the LRM, and what we call “deferred” is called “deferred immediate” or
just “deferred” in the LRM. The LRM uses “immediate” to mean either “simple immediate” or
“deferred immediate”, but we will use the phrase “immediate or deferred” for this union. We find
our terminology clear and less verbose than the LRM, and there is usually no confusion in context
about the kind or kinds of assertions being discussed.