Procedural Concurrent Assertions - SVA: The Power of Assertions in SystemVerilog - page 328

else $display("d_in=%h, clk=%b", d_in, clk);

end

2.

always @( edge clk) begin
if (clk)
a <= a_in;
else
b <= a_in;

end

3.

always @(( posedge clk iff en) or negedge rst_n) begin
if (!rst_n)
a<=0;
else if (!en) $error("en expected");
else
a <= d_in;

end

4.

always @(( posedge clk iff en) or negedge rst_n) begin
if (!en) $error("en expected");
else
a <= d_in;

end

5.

always @( posedge clk) begin
a <= d_in;
@( negedge clk) b <= d_in;

end

6.

always @(ev iff en) begin
a <= d_in;

end

7.

always @(CLK or negedge rst_n) begin
if (!rst_n)
a<=0;
else
a <= a_in;

end

8.

always @(CLK or (ev iff en)) begin
a <= a_in;

end

14.3. A shift register sh has data width W and depth D . Whenever load is true, the
entries of sh shift up one index, with new data shifted into entry sh[0] from d_in
and the last data in entry sh[D-1] shifted out to d_out . Code for the shift register
is shown below:

logic clk, load;
logic [W] d_in, d_out;
logic [D][W] sh;