Resets - SVA: The Power of Assertions in SystemVerilog - page 297

10 20 30 40 50 60 70 80 90 100

clk

retry

bad

a

b

Fig. 13.10 Waveform for a_sync_accept_reject

13.2 Further Details of Resets

This section covers a few further details of specifying resets.

13.2.1 Generalities of Reset Conditions

The examples of reset conditions so far in this chapter have been simple references
to variables or nets. Reset conditions can be general expressions, with the following
provisos:
1. Reset conditions may not reference assertion local variables.
2. A disable condition may reference a sequence instance to which the sequence
method triggered is applied. An abort condition may not make such a
reference.
3. If a reset condition references a sampled value function other than $sampled ,
then the clock of the sampled value function must be explicitly specified.
4. Reset conditions may not contain instances of sequences to which the sequence
method matched is applied.
The rationale for the first rule is that the meaning of such a reference may be
unclear at the beginning of evaluation or as subevaluation threads create copies of
local variables and assign independent values to them. The second rule reflects the
fact that the sampled value of triggered is not useful—it is always 1'b0 .The
third and fourth rules echo the fact that the asynchronous reset conditions are not
governed by a clock. 3
As an example of a more general reset condition, suppose that design reset is
synchronous and occurs only if the sampled value of reset is 1'b1 in a time step

3 These rules exist in the LRM [ 8 ], although they could be relaxed for synchronous aborts.