Clocks - SVA: The Power of Assertions in SystemVerilog - page 273

module various_clocks( input logic clk1, clk2, a, b, c);

1

default clocking NCLK1 @( negedge clk1); endclocking

2

clocking PCLK2 @( posedge clk2); endclocking

3

a2: assert property (a |=> b);

4

a3: assert property (a[ * 2] |=> c);

5

module nested_1;

6

default clocking PCLK2;

7

a4: assert property (a |=> b);

8

endmodule

9

module nested_2;

10

a9: assert property (a |=> @PCLK2 c);

11

endmodule

12

endmodule

13

Fig. 12.11 Module and nested modules with default clocking declarations

The scope of a default clocking declaration is the entire module, interface, program,
or checker in which it appears, including nested declarations of modules, interfaces,
or checkers. A nested module, interface, or checker may, however, have its own
default clocking declaration, which overrides a default from outside. The scope of a
default clocking declaration does not descend into instances of modules, interfaces,
or checkers.
The clocking event of a default clocking block will be called the default clocking
event , or simply the default clock . Throughout the scope of a default clocking
declaration, the default clock applies to all cycle delay operations whose clocking is
not otherwise specified. In particular, the default clock serves as the leading clock of
all concurrent assertions whose leading clock is not explicitly specified or otherwise
inferred (see Sect. 14.2 for rules of inference of clocks for procedural concurrent
assertions).
If the default clock is the leading clock for a concurrent assertion, then the rules
of clock flow (see Sect. 12.2.4.1 ) determine what subsequent parts of the concurrent
assertion are also clocked by the default clock. If the concurrent assertion has no
explicit or otherwise inferred clocking event, then it is singly clocked by the default
clock.
Figure 12.11 shows a variant of module various_clocks that illustrates these
ideas. a2 and a3 are singly clocked by the default clock NCLK1 . Module nested_1
has its own default clock, so a4 is singly clocked by PCLK2 . Module nested_2
inherits the default clock NCLK1 from its parent. a9 is multiply clocked. Its leading
clock is the default clock NCLK1 , but its consequent is clocked by PCLK2 .
A default clock does not apply to declarations of sequences or properties. Clock
scoping rules apply to instances of such declarations in the context of instantiation.