Hardware Reference
In-Depth Information
System
Specification
High level
model
High level model
validation
RTL model
verification
RTL model
Equivalence
checking
Gate level
model
Timing
verification
Post-silicon
Validation
Chip model
Fig. 1.5
High-level design and validation flow
For each design stage, there is a related verification stage which checks the design
correctness at the corresponding level of abstraction. Below we discuss the role of
assertions at the relevant design and verification stages.
1.2.1
Using Assertions for High Level Model
The design specification is a document usually written in a natural language
describing its architecture and functionality. This document normally includes the
main design components, data formats and communication protocols. Below is a
typical example of a specification:
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