Clocks - SVA: The Power of Assertions in SystemVerilog - page 261

Chapter 12
Clocks

The only reason for time is so that everything doesn't happen
at once.

— Albert Einstein

Concurrent assertions are fundamentally temporal in nature. The evaluation of a
concurrent assertion, and of its constituent subsequences and subproperties, evolves
over time in a discrete way. Clocks , or, more precisely, clocking events ,arethe
constructs that define the discretization of time. Clocking events form a rich
subset of general SystemVerilog events. These include familiar edge events, such
as posedge clk , declared events, as well as more general and complex event
expressions.
In SVA, clocking events are declarations with scopes, not operators. As such, they
do not have strengths. Rather, they determine the measurement of time and the times
of evaluation of operators and expressions within their scopes. Within the scope of a
clocking event, one unit, or cycle , of discrete time is measured from one occurrence
of the clocking event to the next. Occurrences of a clocking event are also called
ticks of the clock ,orsimply clock ticks . The intervals between successive clock
ticks can be regular or irregular in length, but in all cases they constitute one unit
of discrete time. This reckoning gives meaning to operators such as ##1 , |=> , and
nexttime , whose semantics involves the notion of the “next point in time”. The
leading clocking event of a concurrent assertion, together with the context in which
the assertion is written, determine when evaluation attempts of the assertion begin.
This chapter discusses the mechanics of declaring clocks and the rules that
determine their scoping, including default clocking. Many concurrent assertions
of practical interest are singly clocked , meaning that all parts of the assertion are