Advanced Sequences - SVA: The Power of Assertions in SystemVerilog - page 256

task run_test;
// ...
endtask : run_test

typedef enum bit [1:0] {NONE, NORMAL, SLOW, FAST} Mode;

program test( input logic clk, ready, pswitch, Mode pmode, ...);
// ...
sequence operational;
@( posedge clk) pswitch && pmode == NORMAL ##1 !pswitch[ * ]
##0 ready;
endsequence : operational

initial begin
wait (operational.triggered);
run_test;
$display("Test started");
// ...
end
endprogram : test

Fig. 11.15 Using level-sensitive sequence event control in programs

When control flow reaches the wait statement, process execution is suspended until
operational.triggered becomes true.
wait statement with sequence triggered is more verbose than sequence event
control, but it may be more convenient when awaiting a Boolean expression
containing a sequence triggered method to become true.
Example 11.33. Suspend the execution of the code until the command is complete
(sequence command_compete has a match) or until an interrupt intr is asserted.
Solution:

t

wait (command_complete.triggered || intr);

11.3.3 Event Semantics of Sequence Match

Like assertions, sequences are also evaluated in the Observed region in much the
same way. Sequence match points play a significant role in assertions as well as
in other descriptions. Two situations are of particular importance. One is when a
sequence match is used as a subexpression subsidiary to the assertion evaluation,
whose result is used as a Boolean value true or false in the enclosing expression.
The other situation is when it appears as an event control, likely used as a trigger for
a process or a delayed statement.