Advanced Sequences - SVA: The Power of Assertions in SystemVerilog - page 255

task run_test;
// ...
endtask : run_test

typedef enum bit [1:0] {NONE, NORMAL, SLOW, FAST} Mode;

program test( input logic clk, ready, pswitch, Mode pmode, ...);
// ...
sequence operational;
@( posedge clk) pswitch && pmode == NORMAL ##1 !pswitch[ * ]
##0 ready;
endsequence : operational

initial begin
@operational;
run_test;
$display("Test started");
// ...
end
endprogram : test

Fig. 11.14 Using sequence event control in programs

￿ The sequence may have many matches, but only the first one will have an effect in
this specific case: when the sequence matches for the first time, the task run_test
is executed, and control flow never returns to this point.

Sequence Event Controls in Modules and Interfaces. Sequence event control
usage is not limited to programs only, it can also be used in modules and interfaces.
Using sequence controls in modules may sometimes greatly simplify the design—
it is similar to the situation with assertions, between their SVA specification and
their manual implementation in procedural form. Unfortunately, industrial synthesis
tools do not support this construct; therefore, the value of using it in modules
and interfaces is only in nonsynthesizable (more abstract) models. However, using
sequence event controls may be convenient in checkers.

11.3.2 Level-Sensitive Sequence Control

The execution of procedural code may be delayed until some event happens, using
wait statement. The wait statement can also be used with the sequence method
triggered (but not matched !).
For example, the code in Fig. 11.14 can be rewritten using the wait statement as
shown in Fig. 11.15 .