Introduction - SVA: The Power of Assertions in SystemVerilog - page 5

module reqgranted1( input logic req, grant, clk);
bit [2:0] ctr = '0;
always @( posedge clk) begin
if (req) ctr <= 1;
else if (ctr > 0 && ctr < 4) ctr <= ctr + 1;
else if (ctr == 4) begin
if (!grant) $display("Request not granted.");
ctr <= '0;
end
end
endmodule : reqgranted1

Fig. 1.2 Checking nonoverlapping evaluations

Fig. 1.3 Two requests before grant

module reqgranted2( input logic req, grant, clk);
bit [3:0] sreg = '0;
always @( posedge clk) begin
sreg <= {sreg, req};
if (sreg[3] && !grant) $display("Request not granted.");
end
endmodule : reqgranted2

Fig. 1.4 Checking overlapping evaluations

is to activate a counter when req is detected, and when the counter value becomes
4, check for grant , as shown in Fig. 1.2 .
What happens if there are two req issued before the first grant is seen, as shown
in Fig. 1.3 ? We would expect our checker to fail because the first request is not
granted. But, instead, the checker will pass. When the second req comes, we reset
the counter and start counting anew—when we wrote the checker we did not think
about overlapping evaluations!
To take overlapping evaluations into account we can use a shift register instead of
a counter, as shown in Fig. 1.4 . When req is asserted it is fed into the shift register
sreg . The Most Significant Bit (MSB) of sreg is set into 1 when there was a req
four cycles ago, and therefore grant must be asserted in this case.