Checkers - SVA: The Power of Assertions in SystemVerilog - page 214

1. The window has been opened

2. The window has been closes

3. The number of clock cycles in the window

￿ to_assume —elaboration time constant indicating that the property about the
window condition should be assumed. By default the property must be asserted.

Notes.

1. Consult Sect. 11.2.1 to handle the case when complete is an arbitrary sequence.

Alternatively, you can implement the simplified version of this checker assuming
that complete is a signal.

2. Coverage constructs are described in Chaps. 4 and 18 .