Checkers - SVA: The Power of Assertions in SystemVerilog - page 208

difficulty to automatically infer a type of the output argument. This limitation is
annoying because it prevents checkers with output arguments to be generic.

Example 9.26. The following checker is illegal because its output argument out
has been left untyped:

checker out_illegal (in, output out, input event clk);
always_ff @clk
out <= in;
endchecker : out_illegal
If we know that the type of b is logic [7] , we can obviously rewrite this checker
like this:

checker out_concrete (in,
output logic [7] out,
input event clk);

always_ff @clk
out <= in;
endchecker : out_concrete
The drawback of this implementation is that the generality has been lost. One
workaround could be to declare the argument out of a size large enough to suit are
needs, for example, 32 bits: logic [32] out . A better workaround would be using
the type construct within out declaration:
checker out_inferred (in,
output var type (in) out,
input event clk);

always_ff @clk
out <= in;
endchecker : out_inferred
Here it is explicitly stated that the type of out should be the same as the type of
in , and the concrete type of in is inferred from the checker instantiation context.

t

9.5.1.2 Checker Output Argument Initialization

Since assignments in initial procedures in checkers are illegal, the only place of
assigning an initial value to a checker output argument, like to any other checker
variable, is at its declaration. The syntax of a checker output argument initialization
is the same as for specifying a default value for an input checker argument.

Example 9.27. The output argument out in the checker out_inferred from
Example 9.26 has not been explicitly initialized. According to the default initial-
ization rules in SystemVerilog, the initial value of out will be '0 if its actual type is