Checkers - SVA: The Power of Assertions in SystemVerilog - page 200

9.3.3 Checker Binding

Sometimes it is desirable to keep verification code separate from the design code.
For example, a validator may want to write several checkers verifying DUT behavior
without modifying RTL (see Sect. 1.2.2 ). SystemVerilog allows external checker
binding to modules or interfaces using the bind directive. It is forbidden to bind
anything to a checker, not even another checker. Essentially, SystemVerilog allows
to bind other design elements, such as modules and interfaces as well in a similar
way, but we will limit our description to checker binding.
It is possible either to bind a checker to all instances of a module or interface, or
to choose only specific instances where the checker is to be bound.
The following syntax is used to bind a checker to all instances of a module:

bind module_name checker_name checker_inst(args);

The following syntax is used to bind a checker to a specific instance of a module:

bind module_inst checker_name checker_inst(args);

To bind a checker to several instances of a module, the module instances should
be separated by commas:

bind module_name: module_inst_1, ..., module_inst_n
checker_name checker_inst(args);

Binding a checker has the same effect as if it were instantiated at the very end
of the target module or interface. If several checkers are bound to the same module
(interface), then the order of instantiation is arbitrary.

Example 9.18. Consider a module trans instantiated three times in the top-level

module top :
module top;
logic clock, snda, sndb, sndc, rcva, rcvb, rcvc;
...
trans ta(clock, snda, rcva);
trans tb(clock, sndb, rcvb);
trans #(2) tc(clock, sndc, rcvc);
endmodule : top
module trans #(DEL=1) ( input logic clock, in,
output logic out);
if (DEL == 1) begin :b
always @( posedge clock)
out <= in;

end
else begin :b
logic [DEL - 2: 0] tmp;
always @( posedge clock) begin
tmp[0] <= in;
for ( int i=1;i<DEL-1;i++)
tmp[i] <= tmp[i - 1];