Let, Sequence and Property Declarations; Inference - SVA: The Power of Assertions in SystemVerilog - page 162

restricted to the event type and the integral types allowed in assertions, and may
be typed or untyped. If untyped, the actual argument expression is enclosed in
parentheses before substitution in the place of the formal argument. The extra pair
of parentheses is added to preserve the precedence of evaluation as indicated by
the parent expression containing the let instance. If the formal argument is typed,
then the self-determined type of the result of the evaluation of the actual argument
must be type cast compatible. Provided that the types are compatible, the actual
expression is cast to the type of the formal argument before being substituted in
place of the occurrences of the formal arguments in the let body.
The following example shows the use of an untyped formal argument.

Example 8.2.
let orReduct(x) = |x;
module m;
logic [2:0] sel;
logic [7:0] [1:0] data;
logic a, b, v, w;
assign v = a && orReduct(sel);
assign w = orReduct(data);
//...
endmodule
After substitution, the code takes the following form:
module m;
logic [2:0] sel;
logic [7:0] [1:0] data;
logic a, b, v, w;
assign v = a && (|sel);
assign w = (|data);
//...
endmodule

t

In the above example, notice that, because the formal is untyped, there is more
latitude in using actual argument expression of different types in the let instance;
no type conversion is performed and the validity of the substituted expression is
completely determined by the expression within which it is substituted.
The formal arguments can also have a default actual argument. When no actual
argument is provided in a let instance, the default one is used. The following
example is similar to the preceding one except that the let is now defined inside
the module and the formal argument x has a default actual expression sel . The first
instance does not provide an actual argument, hence the default sel is taken. The
result is the same as in the preceding example.

Example 8.3.
module m;
logic [2:0] sel;
logic [7:0] [1:0] data;
logic a, b, v, w;
let orReduct(x = sel) = |x;
assign v = a && orReduct();