Let, Sequence and Property Declarations; Inference - SVA: The Power of Assertions in SystemVerilog - page 160

The following example shows some simple let usage and illustrates the effect of
scoping rules applied to these declarations. They are contrasted with similar macro
declarations.

Example 8.1. Effect of scoping rules.

module m;
logic clk,a,b,c,d;
let let_exp = a && b;

always @( posedge clk) begin :B1
let let_exp = c || d;
a <= let_exp;
b<=a;
end
assign c = let_exp;
assign d=b;
endmodule
There are two let declarations of the same name let_exp , but each having a
different expression associated with the name. The first one is defined in the module
scope, and the second one in the always procedure scope. The variables used in the
expression on the right-hand side of the let declaration must be visible at the point
of declaration. Wherever a let is instantiated the nearest visible let declaration is
used. The expression on the right-hand side of the declaration is substituted in the
place of the instance. Module m definition is thus equivalent to the following code:
module m;
logic clk,a,b,c,d;
always @( posedge clk) begin :B1
a <= c || d;
b<=a;
end
assign c = a && b;
assign d=b;
endmodule
Suppose now that we replace the let declarations by macro definitions. The
original module definition becomes

'define macro_exp a && b
module m;
logic clk,a,b,c,d;
always @( posedge clk) begin :B1
'define macro_exp c || d
a <= 'macro_exp;
b<=a;
end
assign c = 'macro_exp;
assign d=b;
endmodule