Let, Sequence and Property Declarations; Inference - SVA: The Power of Assertions in SystemVerilog - page 159

Chapter 8
Let, Sequence and Property Declarations;
Inference

The beginning of wisdom is to call things by their right names.
— Chinese proverb

In SystemVerilog, modules, programs, interfaces, checkers, functions, and tasks
provide means for reuse, and for abstracting and hiding details. SystemVerilog
assertions provide such means too. This is achieved using parameterized let ,
sequence , and property declarations. Their argument lists as well as instantiation
semantics are quite different from the other reuse features. In addition, certain
kinds of actual arguments can be inferred from the instantiation context. Similar
to sequences and properties, let declarations allow to abstract expressions, making
code more readable and reusable. let can be used anywhere, not only in assertions.
One of their intended uses is for defining reusable parameterizable expressions for
immediate and deferred assertions.

8.1 Let Declarations

let declarations are a way to define parameterizable templates for forming expres-
sions. let can be declared in any declarative scope, wherever variables can be
declared, and can be instantiated wherever expressions can be used. let declarations
are similar to text macros, but they are better adapted for use in SystemVerilog
expressions because they are part of the core language. They follow normal scoping
rules. The formal arguments of a let definition may be typed and can have default
actual arguments. However, there are some practical restrictions to be placed both
on the form of the expression definition and on the arguments, even though they are
not stated explicitly in the SystemVerilog LRM. These will be discussed later in the
section.