Hardware Reference
In-Depth Information
Table 7.10 Control task equivalents
Control task Equivalent representation with $assertcontrol
$asserton( level , list ) $assercontrol(3,15,7, level , list )
$assertoff( level , list ) $assercontrol(4,15,7, level , list )
$assertkill( level , list ) $assercontrol(5,15,7, level , list )
$assertpasson( level , list ) $assercontrol(6,31,7, level , list )
$assertpassoff( level , list ) $assercontrol(7,31,7, level , list )
$assertfailon( level , list ) $assercontrol(8,31,7, level , list )
$assertfailoff( level , list ) $assercontrol(9,31,7, level , list )
$assertnonvacuouson( level , list ) $assercontrol(10,31,7, level , list )
$assertvacuousoff( level , list )
$assercontrol(11,31,7, level , list )
them. If a designer is interested in just turning off final deferred immediate,
$assertcontrol can be invoked with statement type argument of value 8. In the
example below, all final deferred immediate statements will be turned off under
scope top.inst1.s1 .
$assertcontrol(4,8,1,0,top.inst1.s1);
$assertcontrol subsumes functionality provided by all other control
tasks. Table 7.10 shows the equivalent assertion control task representation to
$assertcontrol . In that table level represents the level of hierarchy and list
represents the list of assertions or scopes.
Exercises
7.1.
Write an assertion checking that exactly n bits of a signal are high (low).
7.2.
Write an assertion checking one-cold encoding for four-state value variables.
7.3. It was mentioned in Example 7.9 that invoking system function $sampled in
action blocks of immediate or deferred assertions for reporting purposes will result
in inconsistent messages. Explain why.
7.4. Modify the assertions in Example 7.14 to allow sig either remain unchanged
or change in one bit in consecutive clock cycles. Write two versions of this assertion:
one which does not impose any constraints on the initial value of sig , and the other
requiring sig to be 0 upon the termination of the reset sequence.
7.5.
Rewrite assertion
b1: assert property (@( posedge clk) ##1 $fell(sig) |=> !sig[ * 4]);
from Example 7.21 without using sampled value functions.
7.6. What is the assertion behavior in Example 7.26 if the initial delay ##1 is
dropped? Assume that sig is of type bit .
 
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