Assertion System Functions and Tasks - SVA: The Power of Assertions in SystemVerilog - page 140

Table 7.4 Past values of a

Time $past(a,1,en) $past(a,2,en)
30

relative to
@( posedge clk)

0 0

40 0 0

50 1 0

60 1 0

62 1 0

1 0

70

1 1

80

0 1

90

Therefore, even in the presence of a reset sequence, the initial delay may be
necessary:

a4: assert property (@( posedge clk) disable iff (rst)
nexttime $onehot(sig ^ $past(sig)));
A similar situation occurs when the $assertcontrol system task is used to
disable the assertion execution during the reset sequence (Sect. 7.3.1 )

t

Be careful with handling initial clock ticks when using $past . In many cases,
it requires introducing an initial delay.

Gated Clock. The third argument of $past specifies the gating condition. To
compute a past value relative to a gated clock, the third argument should be
explicitly specified. To compute $past(a, n, en, @clk) , it is necessary to take
the sampled value of a at n clock cycles strictly prior to the current simulation tick,
where only “enabled” clock ticks in which en is true are counted.
Example 7.15. Table 7.4 contains values of $past(a, 1, en, @( posedge clk))
and of $past(a, 2, en, @( posedge clk)) for the waveforms from the tim-
ing diagram shown in Fig. 7.2 . As an example consider simulation time steps
62 and 80. At time 62, the previous clock tick when en was high is at time
40, therefore $past(a, 1, en, @( posedge clk)) is 1—the sampled value of
a at time 40. $past(a, 2, en, @( posedge clk)) at time 62 is the same as
$past(a, 1, en, @( posedge clk)) at time 40, i.e., 0.
$past(a, 1, en, @( posedge clk)) at time 80 is 1—the sampled value of
a at time 70. $past(a, 2, en, @( posedge clk)) at time 80 is the same as
$past(a, 1, en, @( posedge clk)) at time 70. The last enabled clock tick prior
to 70 is at time 40, therefore the result is 1.

t