Assertion System Functions and Tasks - SVA: The Power of Assertions in SystemVerilog - page 135

7.2.1 General Sampled Value Functions

Table 7.2 contains the list of available general sampled value functions. Below we
describe each function in more detail.

Table 7.2 General sampled value functions
Name Description
$sampled Return sampled value of expression
$past Return past value of expression
$rose Check whether expression value rose
$fell Check whether expression value fell
$changed Check whether expression value changed
$stable Check whether expression value remained stable

7.2.1.1 Present Sampled Values

System function $sampled takes an integral expression as its argument, and returns
its sampled value. In most cases expression sampling is done in the Preponed region.
See Appendix A for a detailed definition of expression sampling. Using system
function $sampled in concurrent assertions and in checker always_ff procedures
is redundant since the expressions used there are already sampled as explained in
Sects. 4.4 and 9.2.2.2 .

Example 7.7. The following deferred cover statement prints a message when signal
sig value changes:
c_changed: cover final (sig != $sampled(sig))
$info("\%t: sig value changed", $time);
In this cover statement, the value of sig from the Observed region (which is
normally the final value of sig in the current simulation step) is compared against
$sampled(sig) ,thevalueof sig at the beginning of this simulation tick. If these
values are different, a message is issued. This statement does not work in FV since
in FV all signal values are conceptually sampled (see Chap. 21 ). There are more
conventional ways to detect signal changes in a clock-based design, which work
both in simulation and in FV as explained later in this chapter. t

Example 7.8. As mentioned above, the use of $sampled system function in
concurrent assertions is redundant. Assertion

a1: assert property (@( posedge clk) $sampled(a));
is exactly the same thing as

a2: assert property (@( posedge clk) a);