Assertion System Functions and Tasks - SVA: The Power of Assertions in SystemVerilog - page 134

7.1.4 Number of 1-Bits

System function $countones returns a value equal to the number of bits of its
argument set to 1 .
Example 7.5. The system stores the maximal number of simultaneously active
transmitters in register trmax . The transmitter activity is encoded by vector
transmitters in which each bit represents activity of the corresponding trans-
mitter. Check that the total number of simultaneously active transmitters does not
exceed the number stored in trmax . Assume that all bits of transmitters have
defined values.

Solution:

a_tract: assert property (@( posedge clk)
$countones(transmitters) <= trmax);

t

$onehot0(sig) is equivalent to $countones(sig)<= 1 , $onehot(sig) is
equivalent to $countones(sig)== 1 . We recommend to use a specific system
function, and not $countones whenever possible since it makes the user intent
clearer and may be handled more efficiently by tools. When there is a danger of
incorrect handling of undefined values x and z as 0, $countones function should
be used.

7.1.5 Unknown Bits

System function $isunknown returns 1'b1 if any bit of its argument has the value
x or z .
Example 7.6. All bits of data should have known values (i.e., 0 or 1) when read is

active.

Solution:

a_valid_data: assert property (@( posedge clk)
read |-> !$isunknown(data));

t

7.2 Sampled Value Functions

This section describes Sampled Value Functions (SVF)—system functions access-
ing present, past, and future sampled values of an integral expression. One can
divide sampled value functions into two groups: general sampled value functions,
and global clocking sampled value functions. Although sampled value functions
have a temporal nature, they may be used wherever integral expressions are legal
with some exceptions explained below and in later chapters.