Hardware Reference
In-Depth Information
4.4.
Write four versions of an assumption stating that the signal parity checksum
is 0: immediate, deferred observed, deferred final, and concurrent. Explain the
difference between them.
4.5.
What is the difference between assumptions and restrictions?
4.6.
Is it possible to specify actions with restrictions? Why?
4.7.
What is the purpose of cover statements?
4.8.
What is the difference between assertions and cover statements?
4.9.
What is the difference between property and sequence coverage?
4.10.
Write the following statements:
Two inputs of the block must be mutually exclusive.
Two outputs of the block must be mutually exclusive.
We will conduct our verification session only in case when two inputs of the block
are mutually exclusive.
We want to check that two inputs of the block may be mutually exclusive.
We want to check that two outputs of the block are not necessarily mutually
exclusive.
4.11.
What is the difference between the following statements is simulation and in
formal verification:
p1:
assert property
(@(
posedge
clk)a)$display("a is high");
p2:
assume property
(@(
posedge
clk)a)$display("a is high");
p3:
restrict property
(@(
posedge
clk)a);
p4:
cover property
(@(
posedge
clk)a)$display("a is high");
p4:
cover sequence
(@(
posedge
clk)a)$display("a is high");
4.12.
Develop a small design that if simulated will illustrate a difference in
assertion firing between an observed deferred assertion and a final one having the
same Boolean expression.
Search WWH ::
Custom Search