Digital Signal Processing Reference
In-Depth Information
(a)
(b)
wn
0
()
wn
0
()
xn
0
()
H
()
xm
0
()
G
0
()
xn
()
xm
0
()
↑
M
↓
M
0
f
f
f
f M
/
sM
/
f
f M
s
f
f
s
s
sM
s
s
s
(c)
Xf
()
Xf
0
()
(h)
f
f
f
/2
f
/2
s
s
(d)
(g)
Wf
0
()
Wf
0
()
f
f
f
/2
f
/2
s
s
Xf
0
()
(e)
(f)
Xf
0
()
f
f
f
f M
/(2
)
f
f M
/(2
)
sM
s
sM
s
FIGURE 13.2
Analysis and synthesis stages for channel 0.
(a)
(b)
wn
1
()
wn
1
()
xn
1
()
xn
()
H
1
()
xm
1
()
xm
1
()
↑
G
1
()
M
↓
M
f
f
f
f M
/
sM
/
f
f M
s
f
f
s
s
sM
s
s
s
(c)
Xf
()
Xf
1
()
(h)
f
f
f
/2
f
/2
s
s
(d)
(g)
Wf
1
()
Wf
1
()
f
f
f
/2
f
/2
s
s
Xf
1
()
Xf
1
()
(e)
(f)
f
f
f
f M
/(2
)
f
f M
/(2
)
sM
s
sM
s
FIGURE 13.3
Analysis and synthesis stages for channel 1.
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