Signal Sampling and Quantization - Digital Signal Processing: Fundamentals and Applications - page 40

Table 2.2 Quantization Table for the 3-Bit Bipolar Quantizer (step size ¼ D ¼ðx max x min Þ=2 3 ,
x max ¼ maximum voltage, and

x min ¼x max )

Binary Code Quantization Level x q (V) Input Signal Subrange (V)

000

D D x < : D

4 4 3 5

001

D : D x < : D

3 3 5 2 5

010

D : D x < : D

2 2 5 1 5

011

D : x < : D

1 5 0 5

100

: D x < : D

0 0 5 0 5

101

D : D x < : D

0 5 1 5

110

D : D x < : D

2 1 5 2 5

111

D : D x < : D

3 2 5 3 5

a. Using Equation (2.20) , we get the number of quantization levels as

m

¼ 2 3 ¼ 8 L ¼ 2

b. Applying Equation (2.19) yields

D ¼ 5 0
8

¼ 0:625 volt

D
0:625 ¼ 5:12D, from Equation (2.21) we get
i ¼ round x x min
D

c. When x ¼ 3:2

¼ roundð5:12Þ¼5

From Equation (2.22) , we determine the quantization level as
x q ¼ 0 þ 5D ¼ 5 0:625 ¼ 3:125 volts

d. The binary code is determined as 101, either from Figure 2.29 or Table 2.1 .

After quantizing the input signal x , the ADC produces binary codes, as illustrated in Figure 2.31 .
The DAC process is shown in Figure 2.32 . As shown in the figure, the DAC unit takes the binary
codes from the DS processor. Then it converts the binary code using the zero-order hold circuit to
reproduce the sample-and-hold signal. Assuming that the spectrum distortion due to sample-and-hold
effect can be ignored for our illustration, the recovered sample-and-hold signal is further processed
using the anti-image filter. Finally, the analog signal is produced.
When the DAC outputs the analog amplitude x q with finite precision, it introduces quantization
error defined as

e q ¼ x q x (2.23)