Hardware and Software for Digital Signal Processors - Digital Signal Processing: Fundamentals and Applications - page 448

short coefficient; declaration of 16 bit signed integer
int sample, result; declaration of 32 bit signed integer
MPYHL assembly instruction (signed multiply high low 16 MSB x 16 LSB)
result = (_mpyhl(sample,coefficient) ) <<1;
sample must be shifted left by 16 bits to be stored in the high 16 MSB.
coefficient is the 16 bit data to be stored in the low 16 LSB.
result is shifted left by one bit to get rid of the extended sign bit, and high 16
MSB's are designated for the processed data.
Final result will be shifted down to right by 16 bits before DAC conversion.
sample = (result>>16);
FIGURE 9.30
Some coding notations for the Q-15 fixed-point implementation.
The code for the fixed-point implementation is displayed in Figure 9.29 , and some coding notations
are given in Figure 9.30 .
Note that this chapter has provided only basic concepts and an introduction to real-time DSP
implementation. The coding detail and real-time DSP applications will be treated in a separate DSP
course, which deals with real-time implementations.
9.7 SUMMARY
1. The Von Neumann architecture consists of a single, shared memory for programs and data, a single
bus for memory access, an arithmetic unit, and a program control unit. The Von Neumann
processor operates fetching and execution cycles seriously.
2. The Harvard architecture has two separate memory spaces dedicated to program code and to data,
respectively, two corresponding address buses, and two data buses for accessing two memory
spaces. The Harvard processor offers fetching and executions in parallel.
3. The DSP special hardware units include a MAC dedicated to DSP filtering operations, a shifter unit
for scaling, and address generators for circular buffering.
4. The fixed-point DS processor uses integer arithmetic. The data format Q-15 for the fixed-point
system is preferred to avoid the overflows.
5. The floating-point processor uses floating-point arithmetic. The standard floating-point formats
include the IEEE single precision and double precision formats.
6. The architectures and features of fixed-point processors and floating-point processors were briefly
reviewed.
7. Implementing digital filters in the fixed-point DSP system requires scaling filter coefficients so that
the filters are in Q-15 format, and input scaling for the adder so that overflow during MAC
operations can be avoided.
8. The floating-point processor is easy to code using floating-point arithmetic and develops the
prototype quickly. However, it is not efficient in terms of the number of instructions it has to
complete compared with the fixed-point processor.
9. The fixed-point processor using fixed-point arithmetic takes much effort to code. But it offers the
least number of the instructions for the CPU to execute.