Hardware and Software for Digital Signal Processors - Digital Signal Processing: Fundamentals and Applications - page 438

3. Memory and internal buses: Memory space is divided into internal program memory, internal
data memory, and internal peripheral and external memory space. The internal buses include
a 32-bit program address bus, a 256-bit program data bus to carry out eight 32-bit instructions
(VLIW), two 32-bit data address buses, two 64-bit load data buses, two 64-bit store data
buses, two 32-bit DMA buses, and two 32-bit DMA address buses responsible for reading and
writing. There also is a 22-bit address bus and a 32-bit data bus for accessing off-chip or
external memory.

4. Peripherals:

a. EMIF, which provides the required timing for accessing external memory;
b. DMA, which moves data from one memory location to another without interfering with CPU
operations;
c. Multichannel buffered serial port (McBSP) with a high-speed multichannel serial

communication link;
d. HPI, which lets a host access internal memory;
e. Boot loader for loading code from off-chip memory or the HPI to internal memory;
f. Timers (two 32-bit counters);
g. Power-down units for saving power for periods when the CPU is inactive.

The software tool for the C67x is the Code Composer Studio (CCS) provided by TI. It allows the user
to build and debug programs from a user-friendly graphical user interface (GUI) and extends the
capabilities of code development tools to include real-time analysis. Installation, tutorial, coding, and
debugging information can be found in the CCS Getting Started Guide (Texas Instruments, 2001) and
in Kehtaranavaz and Simsek (2000).
Of particular note is the TMS320C6713 DSK with a clock rate of 225 MHz, which has the
capability to fetch eight 32-bit instructions every 4.4 nanoseconds (1/225 MHz). The functional block
diagram is shown in Figure 9.21 . A detailed description can be found in Chassaing and Reay (2008).

9.6.2 Concept of Real-Time Processing
We illustrate real-time implementation in Figure 9.22 , where the sampling rate is 8,000 samples per
second; that is, the sampling period is T ¼ 1 =f s ¼ 125 microseconds, which is the time between two
samples.
As shown in Figure 9.22 , the required timing includes an input sample clock and an output sample
clock. The input sample clock maintains the accuracy of the sampling time for each ADC operation,
while the output sample clock keeps the accuracy of the time instant for each DAC operation. The time
between the input sample clock n and output sample clock n consists of the ADC operation, algorithm
processing, and the wait for the next ADC operation. The numbers of instructions for ADC and the
DSP algorithm must be estimated and verified to ensure that all instructions have been completed
before DAC begins. Similarly, the number of instructions for DAC must be verified so that DAC
instructions will be finished between the output sample clock n and the next input sample clock n þ 1 .
Timing usually is set up using the DSP interrupts (we will not pursue the interrupt setup here).
Next, we focus on the implementation of the DSP algorithm in a floating-point system for
simplicity. A DSK setup example (Tan and Jiang, 2010) is depicted in Figure 9.23 , while a skeleton
code for verification of the input and output is depicted in Figure 9.24 .