Digital Signal Processing Reference
In-Depth Information
We choose the S factor as S ¼ 16 and we choose A ¼ 2 to scale down the denominator coefficients by half.
Since the second adder output after scaling is
y
s
ðnÞ¼
0:75
B
wðnÞþ
1:49
B
wðn 1Þþ
0:75
B
wðn 2Þ
to avoid second adder overflow we have to ensure that each coefficient is less than 1, along with the sum of the
absolute values:
0:7
B
þ
1:4
B
þ
0:7
B
< 1
Hence B ¼ 4 is selected. We develop the DSP equations as
x
s
ðnÞ¼xðnÞ=16
w
s
ðnÞ¼0:5x
s
ðnÞ0:76wðn 1Þ0:32wðn 2Þ
wðnÞ¼2w
s
ðnÞ
y
s
ðnÞ¼0:1875wðnÞþ0:3725wðn 1Þþ0:1875wðn 2Þ
yðnÞ¼ðB SÞy
s
ðnÞ¼64y
s
ðnÞ
The implementation for cascading the second-order section filters can be found in Ifeachor and
Jervis (2002).
A practical example will be presented in the next section. Note that if a floating-point DS processor
is used, all the scaling concerns should be ignored, since the floating-point format offers a large
dynamic range, so that overflow hardly ever happens.
9.6
DIGITAL SIGNAL PROCESSING PROGRAMMING EXAMPLES
In this section, we first review the TMS320C67x DSK (DSP Starter Kit), which offers floating-point
and fixed-point arithmetic. We will then investigate real-time implementation of digital filters.
9.6.1
Overview of TMS320C67x DSK
In this section, a Texas Instruments TMS320C6713 DSK (DSP Starter Kit) shown in
Figure 9.18
is
chosen for demonstration. This DSK board has an approximate size of 5 x 8 inches, a clock rate of 225
MHz, and a 16-bit stereo codec TLV320AIC23 (AIC23), which deals with analog inputs and outputs.
The onboard codec AIC23 applies sigma-delta technology for analog-to-digital conversion (ADC) and
digital-to-analog conversion (DAC) functions. The codec runs using a 12 MHz system clock and the
sampling rate can be selected from a range of 8 to 96 kHz for speech and audio processing. Other
boards such as a Texas Instruments TMS320C6711 DSK can also be found in the references
(Kehtaranavaz and Simsek, 2001; TMS320C6x CPU and Instruction Set Reference Guide, 1999). The
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