Hardware and Software for Digital Signal Processors - Digital Signal Processing: Fundamentals and Applications - page 406

9.1 DIGITAL SIGNAL PROCESSOR ARCHITECTURE
Unlike microprocessors and microcontrollers, digital signal (DS) processors have special features that
require operations such as fast Fourier transform (FFT), filtering, convolution and correlation, and real-
time sample-based and block-based processing. Therefore, DS processors use a different dedicated
hardware architecture.
We first compare the architecture of the general microprocessor with that of the DS processors. The
design of general microprocessors and microcontrollers is based on the Von Neumann architecture,
which was developed from a research paper written by John Von Neumann and others in 1946. Von
Neumann suggested that computer instructions, as we shall discuss, be numerical codes instead of
special wiring. Figure 9.1 shows the Von Neumann architecture.
As shown in Figure 9.1 , a Von Neumann processor contains a single, shared memory for programs
and data, a single bus for memory access, an arithmetic unit, and a program control unit. The processor
proceeds in a serial fashion in terms of fetching and execution cycles. This means that the central
processing unit (CPU) fetches an instruction from memory and decodes it to figure out what operation
to do, then executes the instruction. The instruction (in machine code) has two parts: the opcode and
the operand . The opcode specifies what the operation is, that is, tells the CPU what to do. The operand
informs the CPU what data to operate on. These instructions will modify memory, or input and output
(I/O). After an instruction is completed, the cycles will resume for the next instruction. One instruction
or piece of data can be retrieved at a time. Since the processor proceeds in a serial fashion, it causes
most units to stay in a wait state.
As noted, the Von Neumann architecture operates the cycles of fetching and execution by fetching
an instruction frommemory, decoding it via the program control unit, and finally executing instruction.
When execution requires data movement d that is, data to be read from or written to memory d the next
instruction will be fetched after the current instruction is completed. The Von Neumann-based
processor has this bottleneck mainly due to the use of a single, shared memory for both program
instructions and data. Increasing the speed of the bus, memory, and computational units can improve
speed, but not significantly.

Address
generator

Program
control unit

Address bus

Arithmetic
unit

Program and
data memory

Input/Output
devices

Data bus

FIGURE 9.1

General microprocessor based on Von Neumann architecture.