Hardware Reference
In-Depth Information
Signaling
The clock polarity determines the idle clock level, while the phase determines whether
the data line is sampled on the rising or falling clock signal. Figure
13-2
shows mode
0,0, which is perhaps the preferred form of SPI signaling. In Figure
13-2
, the slave is
selected first, by bringing the
SS
(slave select) active. Only one slave can be selected at
a time, since there must be only one slave driving the MISO line. Shortly after the slave is
selected, the master drives the MOSI line, and the slave simultaneously drives the MISO
line with the first data bit. This can be the most or least significant bit, depending on how
the controller is configured. The diagram shows the least significant bit first.
Figure 13-2.
SPI signaling, modes 0 and 2
In mode 0,0 the first bit is clocked into the master and slave when the clock line
falls from high to low. This clock transition is positioned midway in the data bit cell. The
remaining bits are successively clocked into master and slave simultaneously as the clock
transitions from high to low. The transmission ends when the master deactivates the slave
select line. When the clock polarity is reversed (CPOL = 1, CPHA = 0), the clock signal
shown in Figure
13-2
is simply inverted. The data is clocked at the same time in the data
cell, but on the rising edge of the clock instead.
Figure
13-3
shows the clock signals with the phase set to 1 (CPHA = 1). When the clock
is noninverted (CPOL = 0), the data is clocked on the rising edge. Note that the clock must
transition to its nonidle state one-half clock cycle earlier than when the phase is 0 (CPHA = 0).
When the SPI mode is 1,1, the data is clocked in on the falling edge of the clock.
