Hardware Reference
In-Depth Information
Many SPI devices support only 8-bit transfers, while others are more flexible. The SPI
bus is a de facto standard, meaning that there is no standard for data transfer width and
SPI mode.
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The SPI controller can also be configured to transmit the most significant or
the least significant bit first. All of this flexibility can result in confusion.
SPI Mode
SPI operates in one of four possible clock signaling modes, based on two parameters:
Parameter
Description
CPOL
Clock polarity
CPHA
Clock phase
Each parameter has two possibilities, resulting in four possible SPI modes of
operation. Table
13-1
lists all four modes available. Note that a given mode is often
referred to by using a pair of numbers like 1,0 or simply as mode 2 (for the same mode, as
shown in the table). Both types of references are shown in the Mode column.
Table 13-1.
SPI Modes
CPOL
CPHA
Mode
Description
0
0
0,0
0
Noninverted clock, sampled on rising edge
0
1
0,1
1
Noninverted clock, sampled on falling edge
1
0
1,0
2
Inverted clock, sampled on rising edge
1
1
1,1
3
Inverted clock, sampled on falling edge
Clock Sense
Description
Noninverted
Signal is idle low, active high
Inverted
Signal is idle high, active low
Peripheral manufacturers did not define a standard signaling convention in the
beginning, so SPI controllers allow configuration to accommodate any of the four modes.
However, once a mode has been chosen, all slaves on the same bus must agree.
