Hardware Reference
In-Depth Information
Multimaster and Arbitration
The I2C protocol does support the idea of multiple masters. This complicates things,
because two masters may grab the bus and transmit at the same time. When this
happens, a process of arbitration is used to resolve the clash.
Each transmitting master simultaneously monitors what it sees on the bus that it
is driving. If a discrepancy is seen between what it is transmitting and what it is sensing
on the bus line, it knows that it must release the bus and cease. The first node to notice
conflict is required to release the bus. The other that has not noticed any discrepancy is
free to continue its transmission, since its message has not been affected. If it too sees a
problem, it will also cease and retry later.
Not all devices support this arbitration. Ones that do are usually advertised as having
multimaster support
. Multimaster arbitration is not covered in this topic, since this is an
advanced I2C topic.
Bus Signaling
The start and stop bits are special in the I2C protocol. The start bit is illustrated in
Figure
12-2
. Notice the SDA line transition from high to low, while the clock remains in
the high (idle) state. The clock will follow by going low after 1/2 bit time following the
SDA transition. This special signal combination informs all connected devices to “listen
up,” since the next piece of information transmitted will be the device address.
Figure 12-2.
I2C start/stop signaling
The stop bit is also special in that it allows slave devices to know whether more
information is coming. When the SDA line transitions from low to high midway through a
bit cell, it is interpreted as a
stop bit
. The stop bit signals the end of the message.
There is also the concept of a
repeated start
, often labeled in diagrams as
SR
. This
signal is electrically identical to the start bit, except that it occurs within a message in
place of a stop bit. This signals to the peripheral that more data is being sent or required
as part of another message.
