Hardware Reference
In-Depth Information
Figure 11-3. 1-Wire read/write of 1 data bit
When a 0 is being transmitted, the line is held low for approximately 60 msec. Then
the bus is released and allowed to return high. When a 1 bit is being transmitted, the line
is held low for only about 6 msec before releasing the bus. Another data bit is not begun
until 70 msec after the start of the previous bit. This leaves a guard time of 10 msec between
bits. The receiver then has ample time to process the bit and gains some signal noise
immunity.
The receiver notices a data bit is coming when the line drops low. It then starts a
timer and samples the bus at approximately 15 msec. If the bus is still in the low state, a 0
data bit is registered. Otherwise, the data bit is interpreted as a 1. Having registered a data
bit, the receiver then waits further until the line returns high (in the case of a 0 bit). The
receiver remains idle until it notices the line going low again, announcing the start of the
next bit.
The sender can be either the master or the slave, but the master always has control.
Slaves do not write data to the bus unless the master has specifically requested it.
Slave Support
Table 11-1 lists the slave devices that are supported by Raspbian Linux. The module
names listed are found in the kernel source directory arch/arm/machbcm2708/slave .
 
Search WWH ::




Custom Search