Hardware Reference
In-Depth Information
Pull-up Resistors
As noted earlier, GPIO pins 2 and 3 have an external resistor tied to the +3.3 V rail. The
remaining GPIO pins are pulled high or low by an internal 50
k
Ω resistor in the SoC.
56, 48
The internal pull-up resistor is rather weak, and effective at only giving an unconnected
GPIO input a defined state. A CMOS input should not be allowed to float midway
between its logic, high or low. When pull-up resistance is needed for an external circuit,
it is probably best to provide an external pull-up resistor, rather than rely on the weak
internal one.
Configuring Pull-up Resistors
The pull-up configuration of a GPIO pin can be configured using the SoC registers GPPUP
and GPPUDCLK0/1. (The “Physical Memory” section of Chapter 4 has the physical
addresses for these registers.)
The GPPUP register is laid out as follows:
GPPUP Register
Bits
Field
Description
Type
Reset
31-2
-
Unused
GPIO pin pull-up/down
R
0
1-0
PUD
00 Off—disable pull-up/down
01 Pull-down enable
10 Pull-up enable
11 Reserved
R/W
0
The GPPUDCLK0 register is laid out as follows:
GPPUDCLK0 Register
Bits
Field
Description
Type
Reset
31-0
PUDCLKn
n = 0..31
R/W
0
0
No effect
1
Assert clock
