Hardware Reference
In-Depth Information
The
pin
connections
and
signals
present
on
the
PCI
bus
connector
are
summarized in the following table:
The PCI expansion bus connector
Pin
Name
Description
Pin
Name
Description
A1
TRST
Test logic reset
B1
12 V
12 V DC
A2
+ 12 V
+ 12 V DC
B2
TCK
Test Clock
A3
TMS
Test mode select
B3
GND
Ground
A4
TDI
Test data input
B4
TDO
Test data output
A5
+ 5V
+ 5 V DC
B5
+ 5V
+ 5V DC
A6
INTA
Interrupt A
B6
+ 5V
+ 5V DC
A7
INTC
Interrupt C
B7
INTB
Interrupt B
A8
+ 5V
+ 5 V DC
B8
INTD
Interrupt D
A9
—-
Reserved
B9
PRSNT1
Present
A10
+ 5 V
Power ( + 5V or + 3.3 V)
B10
—-
Reserved
A11
—-
Reserved
B11
PRSNT2
Present
A12
GND03
Ground or keyway for 3.3 V/
B12
GND
Ground or keyway for 3.3 V/
universal cards
universal cards
A13
GND05
Ground or keyway for 3.3 V/
B13
GND
Ground or open (key) for 3.3 V/
universal cards
universal cards
A14
3.3 V aux
B14
RES
Reserved
A15
RESET
Reset
B15
GND
Ground
A16
+ 5 V
Power ( + 5V or + 3.3 V)
B16
CLK
Clock
A17
GNT
Grant PCI use
B17
GND
Ground
A18
GND08
Ground
B18
REQ
Request
A19
PME#
Power management event
B19
+ 5 V
Power ( + 5V or + 3.3 V)
A20
AD30
Address/Data 30
B20
AD31
Address/Data 31
A21
+ 3.3 V01
+ 3.3 V DC
B21
AD29
Address/Data 29
A22
AD28
Address/Data 28
B22
GND
Ground
A23
AD26
Address/Data 26
B23
AD27
Address/Data 27
A24
GND10
Ground
B24
AD25
Address/Data 25
A25
AD24
Address/Data 24
B25
+ 3.3 V
+ 3.3 VDC
A26
IDSEL
Initialization Device Select
B26
C/BE3
Command, Byte enable 3
A27
+ 3.3 V03
+ 3.3 V DC
B27
AD23
Address/Data 23
A28
AD22
Address/Data 22
B28
GND
Ground
A29
AD20
Address/Data 20
B29
AD21
Address/Data 21
A30
GND12
Ground
B30
AD19
Address/Data 19
+ 3.3 V
+ 3.3 V DC
A31
AD18
Address/Data 18
B31
A32
AD16
Address/Data 16
B32
AD17
Address/Data 17
A33
+ 3.3 V05
+ 3.3 V DC
B33
C/BE2
Command, Byte enable 2
A34
FRAME
Address or Data phase
B34
GND13
Ground
A35
GND14
Ground
B35
IRDY#
Initiator ready
A36
TRDY#
Target ready
B36
+ 3.3 V06
+ 3.3 V DC
A37
GND15
Ground
B37
DEVSEL
Device select
A38
STOP
Stop transfer cycle
B38
GND16
Ground
A39
+ 3.3 V07
+ 3.3 V DC
B39
LOCK#
Lock bus
A40
—-
Reserved
B40
PERR#
Parity error
( continued )
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