Hardware Reference
In-Depth Information
Pin number
Abbreviation
Direction
Signal
Function
C14
D11
I/O
Data 11
Data bus line
C15
D12
I/O
Data 12
Data bus line
C16
D13
I/O
Data 13
Data bus line
C17
D14
I/O
Data 14
Data bus line
C18
D15
I/O
Data 15
Data bus line
D1
/MEMCS16
I
Memory chip
Taken low to indicate that the current data
select 16
transfer is a 16-bit (single wait state)
memory operation
D2
/IOCS16
I
I/O chip select 16
Taken low to indicate that the current data
transfer is a 16-bit (single wait state)
I/O operation
D3
IRQ10
I
Interrupt request
Asserted by an I/O device when it
level 10
requires service
D4
IRQ11
I
Interrupt request
Asserted by an I/O device when it
level 11
requires service
D5
IRQ12
I
Interrupt request
Asserted by an I/O device when it
level 12
requires service
D6
IRQ13
I
Interrupt request
Asserted by an I/O device when it
level 10
requires service
D7
IRQ14
I
Interrupt request
Asserted by an I/O device when it
level 10
requires service
D8
/DACK0
O
Direct memory access
Taken low to acknowledge a DMA request
acknowledge level 0
on the corresponding level
D9
DRQO
I
Direct memory
Taken high when a DMA transfer is
access request
required. The signal remains high until the
level 0
corresponding DACK line goes low
D10
/DACK5
O
Direct memory access
Taken low to acknowledge a DMA
acknowledge level 5
request on the corresponding level
D11
DRQ5
I
Direct memory
Taken high when a DMA transfer is
access request
required. The signal remains high until
level 5
the corresponding DACK line goes low
D12
/DACK6
O
Direct memory access
Taken low to acknowledge a DMA request
acknowledge level 6
on the corresponding level
D13
DRQ6
I
Direct memory
Taken high when a DMA transfer is
access request
required. The signal remains high until the
level 6
corresponding DACK line goes low
D14
/DACK7
O
Direct memory
Taken low to acknowledge a DMA request
access acknowledge
on the corresponding level
level 7
D15
DRQ7
I
Direct memory
Taken high when a DMA transfer is
access request
required. The signal remains high until the
level 7
corresponding DACK line goes low
D16
+
5 V
n.a.
+
5V DC
+
5 V supply voltage
D17
/MASTER
I
Master
Taken low by the I/O processor when controlling
the system address, data and control bus lines
D18
GND
n.a.
Ground
Ground/common 0 V
n.a. indicates 'not applicable.'
