Hardware Reference
In-Depth Information
Pin number
Abbreviation
Direction
Signal
Function
B20
+
5 V
n.a.
+
5V DC
+
5 V supply voltage
B30
OSC
O
14.31818 MHz clock
Fast clock with 70 ns period and 50% duty cycle
B31
GND
n.a.
Ground
Ground/common 0 V
Notes:
1
Signal directions are quoted relative to the system motherboard; I represents input,
O represents output, and I/O represents a bidirectional signal used both for input and
also for output (n.a. indicates 'not applicable').
2
IRQ4, IRQ6, and IRQ7 are generated by the motherboard serial, disk, and parallel
interfaces, respectively.
3
DACK0 (sometimes labelled REFRESH) is used to refresh dynamic memory while
DACK1 to DACK3 are used to acknowledge other DMA requests.
4
A / indicates a signal line that is active low (or asserted low).
The 36-way EISA (PC-AT expansion bus) connector
The PC-AT is fitted with an additional expansion bus connector which provides
access to the upper eight data lines, D8 to Dl5, as well as further control bus
lines. The AT-bus employs an additional 36-way direct edge-type connector.
One side of the connector is referred to as C (lines are numbered C1 to C18)
whilst the other is referred to as D (lines are numbered Dl to D18), as shown in
Figure 2.3. The upper eight data bus lines and latched upper address lines are
grouped together on the C-side of the connector (together with memory read
and write lines) while additional interrupt request, DMA request, and DMA
acknowledge lines occupy the D-side.
The following table describes each of the signals present on the 32-way EISA
expansion bus connector:
Pin number
Abbreviation
Direction
Signal
Function
C1
SBHE
I/O
System bus high
When asserted this signal indicates
enable
that the high byte (D8 to D15) is
present on the data bus
C2
LA23
I/O
Latched address 23
Address bus line
C3
LA22
I/O
Latched address 22
Address bus line
C4
LA21
I/O
Latched address 21
Address bus line
C5
LA20
I/O
Latched address 20
Address bus line
C6
LA19
I/O
Latched address 19
Address bus line
C7
LA18
I/O
Latched address 18
Address bus line
C8
LA17
I/O
Latched address 17
Address bus line
C9
/MEMW
I/O
Memory write
Taken low to signal a memory write
operation
C10
/MEMR
I/O
Memory read
Taken low to signal a memory read
operation
C11
D8
I/O
Data 8
Data bus line
C12
D9
I/O
Data 9
Data bus line
C13
D10
I/O
Data 10
Data bus line
(
continued
)
