Hardware Reference
In-Depth Information
Pin number
Abbreviation
Direction
Signal
Function
B7
12 V
n.a.
12 V DC
12 V supply voltage
B8
0WS
I
Zero wait state
Indicates to the processor that the present bus
cycle can be completed without any
additional wait cycles
B9
+ 12 V
n.a.
+ 12 V DC
+ 12 V supply voltage
B10
GND
n.a.
Ground
Ground/common 0 V
B11
/MEMW
O
Memory write
Taken low to signal a memory write
operation
B12
/MEMR
O
Memory read
Taken low to signal a memory read
operation
B13
/IOW
O
I/O write
Taken low to signal an I/O write operation
B14
/IOR
O
I/O read
Taken low to signal an I/O read operation
B15
/DACK3
O
Direct memory
Taken low to acknowledge a DMA request
access acknowledge
on the corresponding level (see notes)
level 3
B16
DRQ3
I
Direct memory
Taken high when a DMA transfer is required.
access request
The signal remains high until the
level 3
corresponding /DACK line goes low
B17
/DACK1
O
Direct memory
Taken low to acknowledge a DMA request
access acknowledge
on the corresponding level (see notes)
level 1
B18
DRQ1
I
Direct memory
Taken high when a DMA transfer is
access request
required. The signal remains high until the
level 1
corresponding /DACK line goes low
B19
/DACK0
O
Direct memory
Taken low to acknowledge a DMA request
access acknowledge
on the corresponding level (see notes)
level 0
B20
CLK4
O
4.77 MHz clock
Processor clock divided by 3 with 210 ns
period and 33% duty cycle
B21
IRQ7
I
Interrupt request
Asserted by an I/O device when it requires
level 7
service (see notes)
B22
IRQ6
I
Interrupt request
Asserted by an I/O device when it requires
level 6
service (see notes)
B23
IRQ5
I
Interrupt request
Asserted by an I/O device when it requires
level 5
service (see notes)
B24
IRQ4
I
Interrupt request
Asserted by an I/O device when it requires
level 4
service (see notes)
B25
IRQ3
I
Interrupt request
Asserted by an I/O device when it requires
level 3
service (see notes)
B26
/DACK2
O
Direct memory
Taken low to acknowledge a DMA request
access acknowledge
on the corresponding level (see notes)
level 2
B27
TC
O
Terminal count
Pulse high to indicate that a DMA transfer
terminal count has been reached
B28
ALE
O
Address latch enable
A falling edge indicates that the address
latch is to be enables. The signal is taken
high during DMA transfers
( continued )
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