The PC - PC Based Instrumentation and Control - page 33

Table 1.12 Representative chipset data

Supported Supported Maximum Bus

Typical DRAM DRAM density memory size ECC/ speeds PCI clock

Chipsets CPUs types (Mbit) supported parity AGP (MHz) dividers

Intel 850 Pentium 4 RDR DC 128 2 GB ECC 1x 100 1/3

(Tehama) PC800 256 2x ( 4) 1/4

[82850] 4x PCI 2.2

(MCH) 1.5v

[82801BA]
(ICH2)
[82802]
(FWH)
SiS 645 Pentium 4 SDRAM 16 3 GB No 1x 100 1/3

[645] PC133 64 2x ( 4) PCI 2.2

[961] DDR PC2700 128 4x

Mem = 4/3 256

Bus 512

Mem = 5/3
Bus

ALi MAGiK 1 Athlon SDRAM 16 3 GB ? 1x 100 1/3

[M1647] Duron PC133 64 2x ( 2) 1/4

[M1535D + ] DDR PC2100 128 4x 133 Asynchronous

Asynch Mem 256 ( 2) PCI 2.2

512

AMD 750 Athlon SDRAM 16 768 MB ECC 1x 100 1/3

[751] Duron PC100 64 2x ( 2) PCI 2.2

(Irongate) 128

[756] (Viper)
AMD 760 Athlon DDR PC2100 64 2 GB ECC 1x 100 1/3

[761] Duron Reg DDR 128 4 GB Reg. 2x ( 2) 1/4

(Irongate-4) 256 4x 133 PCI 2.2

[766] 512 ( 2)

VIA KT-266 Athlon SDRAM 64 3 GB S Both 1x 100 1/3

[VT8366] Duron PC133 128 4 GB Reg. 2x ( 2) 1/4

[VT8233] Reg. SDRAM 256 4x 133 Pseudosynchronous

( 2) VC SDRAM 512 PCI 2.2

DDR PC2100
Reg. DDR
Mem = 3/4
Bus
Mem = 4/3
Bus
Mem = AGP

Another arrangement is shown in Figure 1.16. This architecture uses a North
Bridge and South Bridge (both separate chips within the chipset). The North
Bridge provides the processor with an interface to the memory bus, advanced
graphics port bus (AGP) - see Chapter 2 - and the PCI expansion bus. The South