Hardware Reference
In-Depth Information
Figure 13.20 Logic probe circuit
condition. In the case of a line which is being pulsed, the logic 0 and 1 indicators
will both be illuminated (though not necessarily with the same brightness)
whereas, in the case of a tri-state line neither indicator should be illuminated.
Logic probes generally also provide a means of displaying pulses having a
very short duration which may otherwise go undetected. A pulse stretching
circuit is usually incorporated within the probe circuitry so that an input pulse
of very short duration is elongated sufficiently to produce a visible indication
on a separate pulse LED.
Logic probes invariably derive their power supply from the circuit under test
and are connected by means of a short length of twin flex fitted with insulated
crocodile clips. While almost any convenient connecting point may be used, the
leads of an electrolytic + 5 V rail decoupling capacitor fitted to an expansion
card make ideal connecting points which can be easily identified.
A typical logic probe circuit is shown in Figure 13.20. This circuit uses a
dual comparator to sense the logic 0 and 1 levels and a timer which acts as
a monostable pulse stretcher to indicate the presence of a pulse input rather
than a continuous logic 0 or 1 condition. Typical logic probe indications and
waveforms are shown in Figure 13.21.
Figure 13.22 shows how a logic probe can be used to check a typical com-
binational logic arrangement. The probe is moved from node to node, and the
logic level is displayed and compared with the expected level.
Logic pulsers
It is sometimes necessary to simulate the logic levels generated by a peripheral
device or sensor. A permanent logic level can easily be generated by pulling
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