Hardware Reference
In-Depth Information
The Intel processor family uses a table of 256 4-byte pointers stored in the
bottom 1 KB of memory (addresses 0000H to 03FFH). Each of the locations in
the Interrupt Pointer Table can be loaded with a pointer to a different interrupt
service routine. Each pointer contains 2 bytes for loading into the Instruction
Pointer (IP). This allows the programmer to place his/her interrupt service
routines in any appropriate place within the 1 MB physical address space.
The Pentium family of processors
Initially running at 60 MHz, the Pentium could achieve 100 MIPS. The original
Pentium had an architecture based on 3.2 million transistors and a 32-bit address
bus like the 486 but a 64-bit external data bus. The chip was capable of operation
at twice the speed of its predecessor, the '486 (Figure 1.7).
The first generation Pentium was eventually to become available in 60, 66,
75, 90, 100, 120, 133, 150, 166, and 200 MHz versions. The first ones fitted
Socket 4 boards whilst the rest fitted Socket 7 boards (see Photo 1.6). The
Pentium was
super-scalar
and could execute two instructions per clock cycle.
With two separate 8 KB caches it was much faster than a '486 with the same
clock speed.
The Pentium Pro incorporated a number of changes over the Pentium which
made the chip run faster for the same clock speeds. Three instead of two instruc-
tions can be decoded in each clock cycle and instruction decoding and execution
are decoupled, meaning that instructions can still be executed if one pipeline
stops. Instructions could also be executed out of strict order. The Pentium Pro
had an 8 KB level 1 cache for data and a separate cache for instructions. The
chip was available with up to 1 MB of onboard level 2 cache which further
Photo 1.6
Socket 7 (with lever raised ready to accept a processor)
