Hardware Reference
In-Depth Information
Table 1.5
8088/8086 signal lines
Signal
Function
Notes
AD0-AD7 (8088)
Address/data bus
Multiplexed 8-bit address/data lines
A8-A19 (8088)
Address bus
Non-multiplexed address lines
AD0-AD15 (8086)
Address/data bus
Multiplexed 16-bit address/data bus
A16-A19 (8086)
Address bus
Non-multiplexed address lines
S0-S7
Status lines
S0-S2 are only available in Maximum Mode and are connected to
the 8288 Bus Controller. Note that status lines S3-S7 all share
pins with other signals.
INTR
Interrupt line
Level-triggered, active high interrupt request input
NMI
Non-maskable
Positive edge-triggered non-maskable interrupt input
interrupt line
RESET
Reset line
Active high reset input
READY
Ready line
Active high ready input
TEST
Test
Input used to provide synchronization with external processors.
When a WAIT instruction is encountered in the instruction stream,
the CPU examines the state of the TEST line. If this line is found
the to be high, processor waits in an 'idle' state until the
signal goes low.
QS0, QS1
Queue status
Outputs from the processor which may be used to keep track of the
lines
internal instruction queue.
LOCK
Bus lock
Output from the processor which is taken low to indicate that the
bus is not currently available to other potential bus masters.
RQ/GT0-RQ/GT1
Request/grant
Used for signalling bus requests and grants placed in the
CL register.
with modular internal architecture. This approach to microprocessor design has
allowed Intel to produce a similar microprocessor with identical internal archi-
tecture but employing an 8-bit external bus. This device, the 8088, shares the
same 16-bit internal architecture as its 16-bit bus counterpart. Both devices were
packaged in 40-pin DIL encapsulations. The CPU signal lines are described in
Table 1.5 while the pin connections for the legacy processor family will be
found later in this chapter in Figure 1.12.
The 8086/8088 can be divided internally into two functional blocks com-
prising an Execution Unit (EU) and a Bus Interface Unit (BIU), as shown in
Figure 1.5. The EU is responsible for decoding and executing instructions,
whilst the BIU pre-fetches instructions from memory and places them in an
instruction queue where they await decoding and execution by the EU.
The EU comprises a general and special purpose register block, temporary
registers, arithmetic logic unit (ALU), a Flag (Status) Register, and control logic.
It is important to note that the principal elements of the 8086 EU remain com-
mon to each of the subsequent members of the x86 family, but with additional
registers with the more modern processors.
The BIU architecture varies according to the size of the external bus. The
BIU comprises four Segment Registers and an Instruction Pointer, temporary
storage for instructions held in the instruction queue, and bus control logic.
