Hardware Reference
In-Depth Information
Microprocessors determine the source of data when it is being read (and the
destination of data when it is being written) by placing a unique address on
the address bus. The address at which the data is to be placed (during a
write
operation
) or from which it is to be fetched (during a
read operation
) can either
constitute part of the memory of the system (in which case it may be within
ROM or RAM) or it can be considered to be associated with an input/output
(I/O) port.
Since the data bus is connected to a number of VLSI devices, an essential
requirement of such chips (e.g. ROM or RAM) is that their data outputs should
be capable of being isolated from the bus whenever necessary. These VLSI
devices are fitted with select or enable inputs which are driven by address
decoding logic (not shown in Figures 1.1 and 1.3). This logic ensures that
several ROM, RAM, and I/O devices never simultaneously attempt to place
data on the bus!
The inputs of the address decoding logic are derived from one, or more, of the
address bus lines. The address decoder effectively divides the available memory
into blocks, each of which correspond to one (or more VLSI device). Hence,
where the processor is reading and writing to RAM, for example, the address
decoding logic will ensure that only the RAM is selected whilst the ROM and
I/O remain isolated from the data bus.
Data transfer and control
The transfer of data to and from I/O devices (such as hard drives) can be arranged
in several ways. The simplest method (known as
programmed I/O
, involves
moving all data through the CPU. Effectively, each item of data is first read into
a CPU register and then written from the CPU register to its destination. This
form of data transfer is straightforward but relatively slow, particularly where
a large volume of data has to be transferred. The method is also somewhat
inflexible as the transfer of data has to be incorporated specifically within the
main program flow.
An alternative method allows data to be transferred 'on demand' in response
to an
interrupt request
. Essentially, an interrupt request (IRQ) is a signal that
is sent to the CPU when a peripheral device requires attention (this topic is
described in greater detail later in this chapter). The advantage of this method
is that CPU intervention is only required when data is actually ready to be
transferred or is ready to be accepted (the CPU can thus be left to perform more
useful tasks until data transfer is necessary).
The final method,
direct memory access
(DMA), provides a means of trans-
ferring data between I/O and memory devices without the need for direct CPU
intervention. Direct memory access provides a means of achieving the high-
est possible data transfer rates, and it is instrumental in minimizing the time
taken to transfer data to and from the hard disk or another mass storage device.
Additional
DMA request
(DRQ) and
DMA acknowledge
(DACK) signals are
necessary so that the CPU is made aware that other devices require access to
the bus. Furthermore, as with IRQ signals, several different DMA channels
must be provided in order to cater for the needs of several devices that may be
present within a system. This topic is dealt with in greater detail later in this
chapter.
